Conventionally, integrated circuit devices, such as memory devices, have been made from wafers of semiconductor material which include a plurality of integrated circuits. After a wafer is made, the circuits are separated from each other by dicing the wafer into small chips. Thereafter, the chips are bonded to carriers of various types, electrically interconnected by wires to leads and packaged.
By way of improvement, high density electronic packaging modules having multiple semiconductor chips have become popular. For example, U.S. Pat. Nos. 4,525,921 and 4,646,128 by Carson et al. disclose structure and fabrication techniques for producing one type of high density electronic processing package. Each of these patents describes a semiconductor chip stack consisting of multiple integrated circuit chips adhesively secured together. A metallized pattern is provided on one of the side surfaces of the stack for electrical connection of the stack to external circuitry. This metallization pattern typically includes both individual contacts and bused contacts. The stack is positioned on an upper surface of a substrate such that electrical contact is made between the stack metallization pattern and a substrate surface metallization pattern.
Traditionally, computer memory systems are assembled from many types of memory chips, such as, DRAMs, SRAMs, EPROMs and EEPROMs. The number of storage devices per memory chip technology generation varies but increases over time with more devices per chip being delivered with each succeeding generation, thereby providing greater memory capacity. When a next generation memory chip becomes available, the number of chips needed to make a given memory system is correspondingly reduced. With fewer memory chips needed, the resultant memory system becomes physically smaller.
Next generation DRAM memory chips have traditionally increased by 4.times.the number of bits compared with the current generation technology. For example, assume that the current generation of memory chips comprises 16 megabit (Mb) chips, then by industry standards the next generation will comprise 64 Mb memory chips. This 4.times.advancement from one generation of memory chip to the next is traditionally accomplished only with corresponding advancement in semiconductor tool and process technologies, for example, sufficient to attain a 2.times.reduction in surface geometries. Due to this interrelationship, a significant interval of time can pass between generations of memory chips. Therefore, a genuine improvement in memory system design and fabrication would be attained if current generation memory chips could be packaged to have the same functions and physical dimensions of an anticipated, next generation memory chip. The integrated memory cube structure and fabrication techniques presented herein provide such an improvement.